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RESEARCH

Semiconductor System Lab

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Overview

Advanced driver assistance system (ADAS) for adaptive cruise control and collision avoidance is strongly dependent upon the robust image recognition technology such as lane detection, vehicle/pedestrian detection and traffic sign recognition. However, the conventional ADAS cannot realize more advanced collision evasion in real environment due to the absence of intelligent vehicle/pedestrian behavior analysis. Moreover, accurate distance estimation is essential in ADAS applications and semi-global matching (SGM) is most widely adopted for high accuracy, but its SoC implementation is difficult due to the massive external memory bandwidth. 
  In this paper, an ADAS SoC with behavior analysis with Artificial Intelligence functions and hardware implementation of SGM is proposed. The proposed SoC has dual-mode operations of high-performance operation for intelligent ADAS with real-time SGM in driving-mode and ultra-low-power operation for black box system in parking-mode. It features 1) task-level pipelined SGM processor to reduce external memory bandwidth by 85.8%, 2) region-of-interest generation processor to reduce 86.2% of computation, 3) mixed-mode intention-prediction engine for dual-mode intelligence, and 4) DVFS control to save 36.2% of power in driving-mode. The proposed ADAS processor achieves 862GOPS/W energy-efficiency and 31.4GOPS/mm2 area-efficiency, which are 1.53× and 1.75× improvements than the state-of-the-art, with 30fps throughput under 720p stereo inputs. 

Implementation results



 
Performance comparison
 
Architecture
 
Features

  - Tile-based Task-level Pipelined Semi-Global Matching Processor (SGMP)

  - Massively-Parallel Intention Prediction Engine (IPE)

  - Mixed-mode Configuration of IPE

  - Robust ROI Generation Processor

  - Workload-Prediction DVFS

Related Papers

  - ISSCC 2016 [pdf]

  - ESSCIRC 2015 [pdf]


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